SPECIFICATIONS
Part Number: DS200UCPBG6A
Manufacturer: General Electric
Country of Manufacture: United States (USA)
Product Type: IO Engine CPU board
Series: Mark V
Availability: In Stock
DS200UCPBG6A is an IO Engine CPU board manufactured by General Electric as a part of the Mark V Series. The daughterboard mounted on STCA in the IO Engines is the IO Engine CPU board (UCPB). The UCPB board includes an 80486DX processor (CPU), two RS-232 serial ports, an ARCNET driver, a single inline memory module (SIMM) socket with DRAM, and flash erasable programmable read-only memory (EPROM) with ROM BIOS and I/O mapped flash EPROM. In each of the IO Engines R1, R2, R3, and R5, one UCPB is fitted.
Functional description
- The UCPB in R2 has a PCM daughterboard fitted for serial connection with FMVED motor controllers. The analog and digital IO data is packaged by the UCPB processor and broadcast over COREBUS. A task schedule directs the transmission of the packets. Information sets are collected into packets and then transferred for usage by other devices.
- Less important information is broadcast in "slow packets," which are transmitted at a pace slower than 100 Hz, while more important information is broadcast in "fast packets," which are broadcast at 100 Hz or every 10 ms. The IO Engine loads the IO Configuration data into the DRAM when an IO core is rebooted by reading it from the IOCFG.AP1 file in the Control Engine flash. The IO Configuration is subsequently written via the 3PL and IONET to the analog IO boards and the digital IO boards, respectively.
- Additionally, the TCEA cards must be reset in order to acquire their most recent.
DS200UCPBG6A Connectors
- ARCNET - COREBUS connection that links the I/O cores to the core via the STCA board mounted on each I/O core.
- COM1 - Terminal Interface Monitor (TIMN) connection via the STCA board mounted on each I/O core. Allows for external monitoring of data specific to each I/O core. RS232 interface signal connection to the STCA board.
- COM2 - Typically not used.
- J1 - Bus connection to the STCA board.
- J3 - Bus connection to the STCA board.
- IDE - Typically not used.
DS200UCPBG6A Features
- It has several programmable read-only memory (PROM) modules and one CPU. A switch block with seven switches and a connector for a dual in-line memory module (DIMM) are also included. Additionally, it has a connector for connecting to another board and a 34-pin connector.
- The microprocessor's firmware and programming instructions are stored in PROM modules. The recommended approach is to utilize the same level of firmware and programming instructions in the replacement GE PC Board to guarantee that the microprocessor performs the same.
- The new board is shipped without PROM modules installed in the sockets. The PROM modules from the outdated board should be inserted into the new board as a fix. It is possible to use hand tools designed specifically for removing and reinstalling PROM modules.
One thing to keep in mind is that static on the board can harm the PROM modules. There are certain steps you can take to make static disappear. The board should be kept in its sealed ESD protection pouch until right before installation.
Hardware Configuration
- On the UCPB board, there are three hardware jumpers. Factory tests are conducted using JP1 and JP3. The 486 local bus speed is chosen by JP2. The suggested way for restarting is to start a hard reboot using the power on/off switch for the particular IO core situated in the core.
- For a certain IO Engine, the COREBUS address is set via DIP switches. Only if serial connection with a GE Industrial Systems motor controller is necessary will the hardware jumpers on the PCM need to be set up as instructed in the FMVED commissioning guide.
Software Configuration
- The WATT/VAR input, three pulse rate inputs, and IO configuration information for the FMVED serial download software are all included in the software product for the IO Engine known as TMIA.
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FREQUENTLY ASKED QUESTIONS
What is DS200UCPBG6A?
DS200UCPBG6A is an IO Engine CPU board manufactured by General Electric as a part of the Mark V Series.
What kind of processor does it possess?
It has a 486DX processor or CPU.
How does the component communicate with the external communications?
The component contains an ARCNET driver for external communications between UCPB and operator interfaces.
Which board is UCPB used with?
It is used in conjunction with the AAHA board.
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